1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems having a next branch table used to provide a next branch address to branch prediction circuitry.
2. Description of the Prior Art
It is known to provide data processing systems within branch prediction circuitry. Such branch prediction circuitry is important in providing a high performance within data processing systems employing deep pipelines as the penalty involved in a branch prediction is large. As branch predictors have increased in accuracy, there has been a corresponding increase in the size and complexity of those branch predictors and an increase in difficulty in maintaining their speed of operation, i.e. a potential processing bottleneck is the time taken for a branch predictor to return its branch prediction after a branch instruction has been identified. This is particularly the case when the branch predictor generates its prediction in dependence upon the branch instruction address of the branch instruction to be predicted as the branch instruction address will not be known until the branch instruction has been identified as a branch instruction. Measures which can decrease or remove processing bottlenecks from data processing systems are advantageous and can allow other relaxations, such as increasing the processing speed or reducing the circuit area (level of parallelism) needed to achieve a desired processing speed.